The present invention relates to the field of electronic circuits, and more particularly, to circuits that include many of the features and advantages of delay locked loops and phase locked loops.
A phase-locked loop (PLL) is a circuit that measures variations in the phase of an input signal. A PLL operates by adjusting the phase of a periodic signal generated by an oscillator. The PLL aligns the phase of the oscillator signal with the phase of the input signal. Variations in the phase of the oscillator signal track variations in the phase of the input signal. When the phase of the oscillator signal and the input signal are perfectly aligned, the two signals are said to be in lock. Typically, a PLL has several programmable frequency dividers that multiply or divide down the frequency of the input signal.
A delay-locked loop (DLL) is a circuit that delays an input signal by an adjustable time period. A DLL generates an output signal using an adjustable delay circuit. The output signal is a time delayed version of the input signal. The DLL automatically adjusts the time delay between the input and output signals to equal approximately one period of the input signal.
Many types of integrated circuits can use either a PLL or a DLL to perform a desired function. For example, programmable logic devices (PLDs) use either a PLL or a DLL to generate on-chip clock signals. A DLL or a PLL circuit can be used to offset the phase of an off-chip clock signal in order to improve either the setup time or the clock-to-output delay of input/output signals (e.g., by anticipating the next clock edge).
Both DLLs and PLLs have advantages and disadvantages. PLLs can be used to generate a stable signal when the input signal has a large jitter. PLLs can also be used to multiply and divide down a clock signal by large integer or by rational ratios.
DLLs have less jitter and drift than PLLs when the incoming clock already has a low jitter. DLLs can also lock and resynchronize more quickly to changes in the phase of the incoming clock signal, and have more robust stability constraints. However, DLLs cannot be easily used to divide or multiply the frequency of the incoming clock signal.
Because some applications can use either a PLL or a DLL to perform a particular function, a design engineer must consider the trade-offs between the advantages and disadvantages of using these two types of circuits. It would therefore be desirable to provide a circuit that can align the phase of an output signal with the phase of an input signal and that has the advantages of both a DLL and a PLL.